In a memory system employing a DDR (Double Data Rate)-I system of an SDRAM (synchronous DRAM) as a memory device, a command/address (CA) system, having a register on a memory module, is used. For example, in a technique employing stub-bus topology for a DQ bus and a clock bus, a clock signal (CLK), which is sent from the chip set or the memory controller, is distributed to plural memory devices arranged on a substrate of each memory module. The command/address signal (CA signal), which is sent from a chip set to a memory module over an external command/address (CA) bus, connected to the memory module, is latched by a command/address register, referred to simply as a register, provided on a memory module substrate. The so latched CA signal then is distributed to the memory devices over an internal CA bus reaching the memory device from the register.
FIG. 13 is a block diagram showing an illustrative structure of a CA bus system employed in the conventional DDR-I system. Referring to FIG. 13, the system includes a chip set 50, and at least one memory module 10, referred to simply as a module. On the module 10, there are provided a phase locked loop circuit (PLL) 30, a register, also termed a CA register 40, and a plural number of DRAMs (dynamic random access memories) 20-1 to 20-n, n being a preset positive integer not less than 2). These components are actuated responsive to a clock signal (CLK) and a command/address signal, also termed CA signal, output from the chip set 50.
The PLL 30 receives the clock signal (CLK) output from the chip set 50 to output a clock signal (CLKd) for the DRAM 20 and a clock signal (CLKr) for the register 40.
The register 40 receives the clock signal (CLKr), output from the PLL 30, and latches the CA signal from the chip set 50 to distribute the latched CA signal over an internal CA bus to the associated DRAMs 20-1 to 20-n. 
The DRAMs 20-1 to 20-n latch the CA signal, output from the register 40, with the clock signal (CLKd) output from the PLL 30.
The clock timing is set so that                the flight time of the clock signal (CLKd) from the PLL 30 to the DRAMs 20-1 to 20-n,         the flight time of the clock signal (CLKr) from the PLL 30 to the DRAMs 20-1 to 20-n, and        the feedback time as from a feedback output of the PLL 30 (Fbout) until a feedback input (Fbin) is equal to one another so that the same phase will be obtained in the inputs to the PLL 30, to the register 40 and to the DRAMs 20-1 to 20-n. That is, the clock timing is set so as to be of an electrically equivalent length.        
FIG. 14 is a timing chart for illustrating the operation of the conventional memory system shown in FIG. 13. Referring to FIG. 14, the clocks at respective input sections of the PLL 30, register 40 and the DRAM 20, that is                the clock input to the PLL 30 (CLKin@PLL of FIG. 14),        the feedback input to the PLL 30 (FBin@PLL of FIG. 14),        the clock input to the register 40 (CLKr@REG of FIG. 14) and        the clock input to the DRAM 20 (CLKr@DRAM of FIG. 14) are of the same phase, with the rise timing of the respective clock signals being at the center of the CA signal in the input unit to the register 40 (Cain@Reg. of FIG. 14) (see the position of the timing t0 in FIG. 14).        
The CA signal, latched in the register 40, gets to the DRAM 20 over a time equal to the delay time tpdf, that is the delay time which elapses as from the time the clock signal (CLKr) is input to the register 40 (see Cain@Reg. at timing t0 in FIG. 14) until the register 40 outputs the CA signal, plus the flight time of the CA signal from the register 40 to the DRAM 20 (see CA@DRAM of FIG. 14). The DRAM 20 latches the oncoming CA signal with the rising edge of the clock signal (CLKd@DRAM of FIG. 14) (see timing t1 of FIG. 14) to take the signal in the DRAM 20.
FIG. 14 shows the timing operation of the clock frequency of 200 MHz (depicted as [200 MHzCLK]. In the generation of the clock frequency of 100 MHz, depicted as [100 MHzCLK], a stabilized operation was guaranteed with this timing.
That is, a sufficiently large margin could be taken of the setup time and the hold time of the CA signal with respect to the clock signal (CLKr) in the register 40, because the rising edge of the clock signal (CLKr) is located in the center timing of the CA signal in the input unit of the register 40.
Moreover, in the DRAM 20, the hold time of the CA signal with respect to the clock signal (CLKd) corresponding to the minimum value tpdf.min of the delay time tpdf could be necessarily guaranteed, as shown as CA@DRAM (Slow case) in FIG. 14. In the 100 MHz class generation, no margin-related problem was raised because the value of tpdf.min is of the order of 3 ns (nanosecond).
In the 100 MHz class (1 clock cycle=10 ns), the value of tpdf.max is of the same order of duration, or approximately 5 ns, for the 0.5 period, so that no problem was raised in connection with the setup time of the CA signal for the clock signal (CLKd).
Thus, by using the same phase for the clock signal at each input section (clock input end) of the PLL 30, register 40 and the DRAM 20, a sufficient margin can be taken for the setup time and the hold time of the CS signal at the register 40 and at the DRAM 20.
For phase matching the clock signal in the clock input section of the PLL 30, register 40 and the DRAM 20, it is basically sufficient to equate                the interconnection length of the clock signal (CLKd) from the PLL 30 to the DRAM 20,        the interconnection length of the clock signal (CLKr) from the PLL 30 to the register 40, and        the interconnection length of a feedback loop from a feedback output (Fbout) to the feedback input (Fbin) of the PLL 30 and hence there were raised no designing difficulties.        